Related Art
Rapid advances in computing technology have made it possible to perform trillions of computational operations each second on data sets that are sometimes as large as trillions of bytes. These advances can be attributed to the dramatic improvements in semiconductor manufacturing technologies which have made it possible to integrate tens of millions of devices onto a single chip.
As semiconductor design enters the deep submicron era, process model accuracy is becoming increasingly important. Inaccuracies in the process model negatively affect the efficacy of downstream applications. For example, inaccuracies in the photolithography process model can reduce the efficacy of optical proximity correction (OPC). Hence, it is generally desirable to improve process model accuracy.
Summary
One embodiment of the present invention provides a system for determining an improved process model that models one or more semiconductor manufacturing processes. The system can receive a test layout and empirical data that is obtained by subjecting the test layout to one or more semiconductor manufacturing processes. Next, the system can generate an accurate process model using the test layout and the empirical data. The process model can use a kernel that can differentiate between 1-D (one dimensional) regions and 2-D (two dimensional) regions in a layout.
In one embodiment, the system can categorize the empirical data into 1-D empirical data and 2-D empirical data. The 1-D empirical data is associated with 1-D patterns and/or regions in the layout, whereas the 2-D empirical data is associated with 2-D patterns and/or regions in the layout. The system can then generate a first process model using the 1-D empirical data. Note that the first process model may not include a 2-D-pattern detecting kernel. Next, the system can generate an improved process model using the first process model, a 2-D-pattern detecting kernel, and the 2-D empirical data.